The present invention generally relates to request cancel systems, and more particularly to a request cancel system for cancelling a request to a memory device.
FIG. 1 generally shows a processing system in which a plurality of central processing units (CPUs) 101.sub.1 through 101.sub.n can access the banks of a main storage unit (MSU) 103 via a memory control unit (MCU) 102. The CPUs 101.sub.1 through 101.sub.n are used as access units.
Conventionally, when accessing to a bank of the MSU 103, which is used in common by the CPUs 101.sub.1 through 101.sub.n, the MCU 102 (having a system structure shown in FIG. 2) controls access requests so that a first access requested by one CPU 101.sub.i and a following second access requested by another CPU 101.sub.j do not access the same bank of the MSU 103.
In FIG. 2, it is assumed for the sake of convenience that the first access is requested by the CPU 101.sub.i and the following second access is requested by the CPU 101.sub.j. A bank busy flag group 21 stores information which indicates whether or not banks of the MSU 103 are in use (that is, "busy") in correspondence with the addresses of the banks. In a first cycle, when the first access request is received by the MCU 102, an address of the first access request is stored in an interface register 22-1 and a request operation code, a request effective signal and other contents of the first access request are stored in an interface register 23-1. Predetermined lower bits of the address which is stored in the interface register 22-1 are decoded by a decoder 24-1 and a decoded address is supplied to a selector 25. This decoded address designates a bank of the MSU 103. The selector 25 outputs a busy flag corresponding to the bank which is designated by the decoded address. This busy flag is supplied to a checking part 26-1 which also receives the predetermined lower bits of the address from the interface register 22-1. The busy flag indicates whether or not the designated bank is busy.
In this case, it is assumed for the sake of convenience that the designated bank is not busy and the check part 26-1 supplies to an AND circuit 27.sub.1 a signal which indicates that the address of the first access request does not match the address of a bank which is busy. An output signal of the AND circuit 27.sub.1 is supplied to a priority controller 28 which controls a selector 29. The priority controller 28 discriminates whether or not to permit the selector 29 to selectively output the request operation code, the request effective signal and other contents of the first access request which are stored in the interface register 23-1, based on the signal from the AND circuit 27.sub.1.
The selector 29 selectively outputs the request operation code from the interface register 23-1 in response to a control signal from the priority controller 28. Hence, the request operation code of the first access request is stored in a PR1 register 30. In addition, the priority controller 28 sets an address selection signal in a PR1' register 31. The output of the PR1 register 30 is supplied to a MSU interface register 39.
Then, in a second cycle, the request operation code of the first access request which is stored in the PR1 register 30 is set in a P1 register 32-1, and the address selection signal which is stored in the PR1' register 31 is supplied to control a selector 33. The P1 register 32-1, a P2 register 32-2 and the like constitute a pipeline PL. The selector 33 selectively outputs the predetermined lower bits of the address which is stored in the interface register 22-1. The predetermined lower bits output from the selector 33 are set in a P1' register 34. In addition, the predetermined lower bits output from the selector 33 are supplied to a decoder 36. The decoder 36 decodes the predetermined lower bits of the address and sets the bank busy signal to the ON state only during this cycle. This bank busy signal prevents the same bank from being selected by the priority controller 28 when the second access request designates the same bank as the first access request. At the same time, an address and a request operation code of the second access request by the CPU 101.sub.j are respectively stored in interface registers 22-2 and 23-2. It is assumed that the address of the second access request is identical to the address of the first access request.
In a third cycle, the request operation code of the first access request which is stored in the P1 register 32-1 is set in the P2 register 32-2, and the predetermined lower bits of the address which are stored in the P1' register 34 are supplied to a decoder 35. The decoder 35 decodes the predetermined lower bits of the address of the first access request and sets the bank busy signal to the ON state only during this cycle. This bank busy signal is supplied to an OR circuit 37 and the bank busy flag set to indicate the busy state. Output signals of the decoders 35 and 36 are supplied to the OR circuit 37, and an output signal of the OR circuit 37 is supplied to an OR circuit 38 which is also supplied with the bank busy flag. Actually, the OR circuit 37 comprises a number of OR gates equal to the number of banks, and the OR circuit 38 also comprises a number of OR gates equal to the number of banks.
At this point in time, it is finally detected from an output signal of the OR circuit 38 that the bank which is designated by the address of the second access request is busy. Hence, the check part 26-2 supplies to the AND circuit 27.sub.2 a signal which indicates that the address of the second access request matches the address of the bank which is busy, and the priority controller 28 prohibits the CPU 101.sub.j from accessing the bank which is busy in response to the output signal of the AND circuit 27.sub.2.
In a fourth cycle and thereafter, the contents of the second access request are not set in the register PR1 30 by the operation of the priority controller 28 based on the busy flag signal which is registered in the bank busy flag group 21.
Although not shown in FIG. 2, the address is supplied to the MSU 103 when the priority controller 28 selects the interface register 22-1 (or 22-2) and sets the address from the selected interface register in the MSU interface register 39.
FIGS. 3(A) through 3(F) are timing charts for explaining the general operation timing of the MCU 102. In FIG. 3(A), cycles PR0i, PR1i, P1i and P2i respectively correspond to the first, second, third and fourth cycles described above for the CPU 101.sub.i. Similarly, cycles PR0j, PR1j and P1j shown in FIG. 3(B) respectively correspond to the second, third and fourth cycles described above for the CPU 101.sub.j. FIGS. 3(C) through 3(F) respectively show the timings of signals at parts 1 through 4 of the MCU 102 shown in FIG. 2. It can be seen from FIG. 3(B) that the second access request is not accepted, that is, cancelled, from the cycle PR1j as indicated by "X" above the cycles. FIG. 3(E) shows a time when the set bank busy flag is output to indicate the busy state of the bank.
Accordingly, when the consecutive first and second access requests access identical banks, it is detected, when the second access request is received, that the designated bank is busy. This detection is made in a path PA indicated by a phantom line in FIG. 2. However, the second access request is only cancelled from the cycle PR1j (third cycle). For this reason, as the scale of the MSU 103 becomes large and/or the number n of CPUs 101.sub.1 through 101.sub.n becomes large, the number of selectors 33, logic circuits such as decoders 35 and 36 and gates in the path PA becomes considerably large. As a result, there is a problem in that the delay time introduced in the path PA becomes large and the time required to detect a bank busy state may exceed one machine cycle of the MCU 102.